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dg421/dg423/dg425 improved low-power, cmos analog switches with latches ________________________________________________________________ maxim integrated products 1 top view 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 s1 in1 v- gnd n.c. n.c. wr d1 dg421 v l v+ in2 s2 d2 rs n.c. n.c. dip _________________pin configurations switches shown for logic "1" input d2 d1 ck r dq ck r dq two spst switches per package wr rs in switch 01 0 1 off on logic "o" 0.8v logic "1" 3 2.4v dg421 truth table s1 wr in1 in2 rs s2 dg421 __functional diagrams/truth tables call toll free 1-800-998-8800 for free samples or literature. 19-0137; rev 1; 3/94 _______________general description maxim? redesigned dg421/dg423/dg425 monolithic analog switches now feature guaranteed on-resistance matching (3 max) between switches and on- resistance flatness over the signal range (4 max). these low on- resistance switches (20 typ) conduct equally well in both directions. they guarantee a low charge injection of 15pc maximum and an esd tolerance of 2000v minimum per method 3015.7. off leakage current over temperature has also been reduced (less than 5na at +85?). the dg421/dg423/dg425 are precision, dual cmos switches with latchable logic inputs that simplify inter- facing with microprocessors (ps). the single-pole/single- throw dg421 and double-pole/single-throw dg425 are normally open dual switches. the dual, single- pole/double-throw dg423 has two normally open and two normally closed switches. fast switching times (175ns for t on and 145ns for t off ) and low power consumption (35? max) make these parts ideal for battery- powered applications requiring ?-compatible switches. operation is from a single +10v to +30v supply, or bipolar 4.5v to ?0v supplies. fabricated with the same 44v silicon-gate process, these switches have rail-to-rail signal handling capabilities. _______________________applications sample-and-hold circuits modems fax machines test equipment battery-operated systems pbx, pabx guidance and control systems military radios audio signal routing communication systems ______________________new features ? plug-in upgrades for industry-standard dg421/dg423/dg425 ? improved r (ds)on match between channels (3 max) ? guaranteed r flat(on) over signal range (4 max) ? improved charge injection (15pc max) ? improved off leakage current over temperature (<5na at +85?) ? withstands electrostatic discharge (2000v min) per method 3015.7 __________________existing features ? low r ds(on) (35 max) ? single-supply operation +10v to +30v bipolar-supply operation ?.5v to ?0v ? low power consumption (35? max) ? rail-to-rail signal handling capability ? ttl/cmos-logic compatible ______________ordering information ordering information continued at end of data sheet. * contact factory for dice specifications. ** contact factory for availability and processing to mil-std-883b. functional diagrams/truth tables continued at end of data sheet. n.c. = no internal connection pin configurations continued at end of data sheet. 16 cerdip** -55? to +125? dg421ak 16 so -40? to +85? dg421dy dice* 0? to +70? dg421c/d 0? to +70? 16 cerdip -40? to +85? dg421dk 16 plastic dip -40? to +85? dg421dj 16 so 0? to +70? dg421cy 16 plastic dip dg421 cj pin-package temp. range part
dg421/dg423/dg425 improved low-power, cmos analog switches with latches 2 _______________________________________________________________________________________ voltage referenced to v- v+............................................................44v gnd .........................................................25v v l .................................. (gnd - 0.3v) to (v+ + 0.3v) digital inputs, v s , v d (note 1) .............. (v- - 2v) to (v+ + 2v) current (any terminal, except s or d) .................................30ma continuous current, s or d .................................................20ma peak current, s or d (pulsed at 1ms, 10% duty cycle max)...100ma continuous power dissipation (t a = +70?) 16-pin plastic dip (derate 10.53mw/? above +70?) . . . 842mw 20-pin plcc (derate 10.00mw/? above +70?) . . . . . 800mw 16-pin cerdip (derate 10.00mw/? above +70?) . . . 800mw operating temperature ranges dg42_c_ .......................................... 0? to +70? dg42_d_ .......................................-40c to +85? dg42_a_ . .....................................-55c to +125? storage temperature ranges dg42_c_/dg42_d_ ...........................-65c to +125? dg42_a_ ..................................... -65c to +150? lead temperature (soldering, 10sec) .................... +300? electrical characteristics (v+ = 15v, v- = -15v, v l = +5v, gnd = 0v, v inh = +2.4v, v inl = +0.8v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under "absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings note 1: signals on s, d, or in exceeding v+ or v- are clamped by internal diodes. limit forward current to maximum current ratings. t a = +25? t a = t min to t max v+ = 13.5v, v- = -13.5v, i s = -10ma, v d = ?0v r ds(on) drain-source on-resistance conditions symbol parameter 20 45 dg42_c, dg42_d min typ max (note 2) units 45 45 20 35 dg42_a min typ max (note 2) t a = +25? t a = t min to t max v+ = 16.5v, v- = -16.5v, i s = -10ma, v d = ?0v d r ds(on) on-resistance match between channels (note 4) 4 4 3 3 t a = +25? t a = t min to t max v+ = 15v, v- = -15v, i s = -10ma, v d = ?v r flat(on) on-resistance flatness (note 4) 5 5 4 4 (note 3) v analog analog signal range v -15 15 -15 15 t a = +25? t a = t min to t max v+ = 16.5v, v- = -16.5v, v d = ?5.5v, v s = 15.5v m i s(off) source-off leakage current (note 5) na -5 5 -10 10 -0.50 -0.01 0.50 -0.25 -0.01 0.25 t a = +25? t a = t min to t max v+ = 16.5v, v- = -16.5v, v d = ?5.5v, v s = 15.5v m i d(off) drain-off leakage current (note 5) na -5 5 -10 10 -0.50 -0.01 0.50 -0.25 -0.01 0.25 t a = +25? t a = t min to t max v+ = 16.5v, v- = -16.5v, v d = ?5.5v, v s = ?5.5v i d(on) drain-on leakage current (note 5) na -10 10 -20 20 -1.0 -0.04 1.0 -0.40 -0.04 0.40 switch
dg421/dg423/dg425 improved low-power, cmos analog switches with latches _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, v- = -15v, v l = +5v, gnd = 0v, v inh = +2.4v, v inl = +0.8v, t a = t min to t max , unless otherwise noted.) t a = +25? t a = t min to t max all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v i+ positive supply current conditions symbol parameter ? units -5.0 5.0 -1.0 0.01 1.0 min typ max (note 2) in = 2.4v, all others = 0.8v i inh input current with input voltage high ? -0.50 0.005 0.50 in = 0.8v, all others = 2.4v i inl input current with input voltage low ? -0.50 0.005 0.50 (note 3) v+, v- power supply range v ?.5 ?0 t a = +25? t a = t min to t max all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v i- negative supply current ? -5.0 5.0 -1.0 -0.01 1.0 t a = +25? t a = t min to t max all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v i gnd ground current ? -5.0 5.0 -1.0 -0.01 1.0 t a = +25? t a = t min to t max figure 2 t on turn-on time ns 300 150 250 200 ns figure 2 t off turn-off time t a = +25? t a = -55? to +125? v s = ?0v, r l = 300 , c l = 35pf, figure 3 t ww latch timing ns 200 200 t a = +25? t a = -55? to +125? t dw 100 100 t a = +25? t a = -55? to +125? t wd 100 60 t a = +25? 525 t a = +25? t a = t min to t max all channels on or off, v+ = 16.5v, v- = -16.5v, v in = 0v or 5v i l logic supply current ? -5.0 5.0 -1.0 -0.01 1.0 break-before-make interval (note 3) t d dg423, figure 4 ns t a = +25? 10 15 charge injection (note 3) q c l = 10nf, v g = 0v, r g = 0 , figure 5 pc t a = +25? 72 off-isolation rejection ratio (note 6) oirr r l = 100 , c l = 5pf, f = 1mhz, figure 6 db t a = +25? 12 drain-off capacitance c d(off) f = 1mhz, figure 8 pf t a = +25? 90 crosstalk (note 7) r l = 50 , c l = 5pf, f = 1mhz, figure 7 db t a = +25? 12 source-off capacitance c s(off) f = 1mhz, figure 8 pf note 2: typical values are for design aid only , are not guaranteed, and are not subject to production testing. the algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. note 3: guaranteed by design. note 4: on-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. flatness is defined as the dif- ference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range. note 5: leakage parameters i s(off) , i d(off) , and i d(on) are 100% tested at the maximum rated hot temperature and guaranteed by correlation at +25?. note 6: off-isolation rejection ratio = 20log (v d /v s ), v d = output, v s = input to off switch. note 7: between any two switches. t a = +25? 39 drain-on capacitance c d(on) f = 1mhz, figure 9 pf t a = +25? 39 source-on capacitance c s(on) f = 1mhz, figure 9 pf input supply dynamic
dg421/dg423/dg425 improved low-power, cmos analog switches with latches 4 _______________________________________________________________________________________ 50 55 20 -20 on-resistance vs. v d (dual-supplies) 25 45 max401-1 v d (v) r ds (on) ( w ) 10 35 30 -10 0 20 40 15 10 5 a: v+ = 5v, v- = -5v b: v+ = 10v, v- = -10v c: v+ = 15v, v- = -15v d: v+ = 20v, v- = -20v a b c d 35 5 -20 on-resistance vs. v d and temperature (dual supplies) 10 30 max401-2 v d (v) r ds (on) ( w ) 20 20 15 -10 10 25 0 v+ = 15v, v- = -15v t a = +125? t a = +85? t a = +25? t a = -55? 140 20 0 on-resistance vs. v d (single supply) 40 120 max401-3 v d (v) r ds (on) ( w ) 20 80 60 515 100 10 v+ = 5v v- = 0v v+ = 10v v+ = 15v v+ = 20v 70 10 0 on-resistance vs. v d and temperature (single supply) 20 60 max401-4 v d (v) r ds (on) ( w ) 20 40 30 515 50 10 v+ = 12v, v- = 0v t a = +125? t a = +85? t a = +25? 100 0.0001 -75 125 off leakage currents vs. temperature 0.001 10 max401-5 temperature (?) off leakage (na) 0.1 0.01 25 1 v+ = 16.5v v- = -16.5v v d = ?5v v s = ?5v 100 0.0001 -75 125 on leakage currents vs. temperature 0.001 10 max401-6 temperature (?) on leakage (na) 0.1 0.01 25 1 v+ = 16.5v v- = -16.5v v d = ?5v v s = ?5v 60 -60 -20 20 charge injection vs. analog voltage -40 40 max401-7 v d (v) q (pc) 10 0 -20 -10 0 20 v+ = 15v, v- = -15v 100 0.0001 -75 125 supply current vs. temperature 0.001 10 max401-8 temperature (?) i+, i-, i l ( m a) 0.1 0.01 25 1 i+ at v+ = 16.5v i- at v- = -16.5v i l at v l = 5v __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.)
dg421/dg423/dg425 improved low-power, cmos analog switches with latches _______________________________________________________________________________________ 5 ___________________pin descriptions 1, 8 d1, d2 drain terminals 2 w r write select 3, 4, 5, 6 n.c. no internal connection 7 r s reset select 9, 16 s1, s2 source terminals 10, 15 in1, in2 input control 11 v+ positive supply 12 v l logic supply 13 gnd ground 14 v- negative supply 1, 8, 3, 6 2, 10, 4, 8 drain terminals 2 3 write select w r 16, 9, 4, 5 20, 12, 5, 7 source terminals s1-s4 7 9 resets select d1-d4 15, 10 19, 13 input control in1, in2 11 14 positive supply v+ r s 12 15 logic supply v l 1, 6, 11, 16 no internal connection n.c. 14 18 negative supply v- 13 17 ground gnd pin name function dip plcc function name figure 1. overvoltage protection using external blocking diodes __________applications information operation with supply voltages other than ?5v the dg421/dg423/dg425 switches operate with ?.5v to ?0v bipolar supplies or with a +10v to +30v single supply. in either case, analog signals ranging from v+ to v- can be switched. the typical operating characteristics graphs illustrate typical analog-signal and supply-voltage on-resistance variations. the usual on-resistance temperature coefficient is 0.5%/? (typ). logic inputs these devices operate with a single positive supply or with bipolar supplies. they maintain ttl compatibility with supplies anywhere in the ?.5v to ?0v range as long as v l = +5v. if v l is connected to v+ or another supply at voltages other than +5v, the devices will operate at cmos-logic-level inputs. overvoltage protection proper power-supply sequencing is recommended for all cmos devices. do not exceed the absolute maxi- mum ratings because stresses beyond the listed rat- ings may cause permanent damage to the devices. always sequence v+ on first, followed by v l , v-, and logic inputs. if power-supply sequencing is not possi- ble, add two small, external signal diodes in series with supply pins for overvoltage protection (figure 1). adding diodes reduces the analog signal range to 1v below v+ and 1v above v-, without affecting low switch resistance and low leakage characteristics. device operation is unchanged, and the difference between v+ and v- should not exceed +44v. v+ d v- s v g dg421 dg423/dg425
dg421/dg423/dg425 improved low-power, cmos analog switches with latches 6 _______________________________________________________________________________________ d -15v ( ) v- r l v out v+ +15v +5v v l gnd v d = 10v for t on v d = -10v for t off in logic input repeat test for in2 and s2. c l includes fixture and stray capacitance. c l switch output s logic input switch output t r < 20ns t f < 20ns v out t off 50% 3v 0v 0v note: logic input waveform is inverted for switches that have the opposite logic sense. dg421 dg423 dg425 v out = v d r l r l + r ds(on) 0.9 x v out 0.9 x v out -v out t on *v d = 10v for t on , v d = -10v for t off figure 2. switching time 3v 0 3v 0 3v 0 v out 0 wr in rs switch output 1.5v t ww t dw t wd 2.0v 0.8v 1.5v t rs t off(rs) 0.8 x v out figure 3. latch timing v out is the steady-state output with the switch on. feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. ______________________________________________timing diagrams/test circuits
dg421/dg423/dg425 improved low-power, cmos analog switches with latches _______________________________________________________________________________________ 7 0ff 0n 0ff v out in q = d v out x c l in dependent on switch configuration. input polarity determined by sense of switch. d v out dg421 dg423 dg425 r g -15v v- v out v+ +15v +5v v g gnd v in = 3v wr d c l 10nf rs v l s in figure 5. charge injection _________________________________timing diagrams/test circuits (continued) d -15v v- r l2 300 w v out1 v+ +15v +5v v l gnd v d = 10v v d = 10v logic input c l includes fixture and stray capacitance. c l2 35pf s logic input switch output 1 switch output 2 0.9 x v out v out1 0.9 x v out t d 50% 3v 0v 0v 0v v out2 t d d r l = 1000 w c l = 35pf s r l1 300 w c l1 35pf rs v out2 dg423 in wr figure 4. dg423 break-before-make interval -15v v- r l gnd wr signal generator +15v v+ 10nf rs +5v v l 10nf d s 0v or 2.4v in dg421 dg423 dg425 v s v d network analyzer figure 6 . off-isolation rejection ratio
dg421/dg423/dg425 improved low-power, cmos analog switches with latches 8 _______________________________________________________________________________________ -15v v- gnd wr +15v v+ 10nf rs +5v v l 10nf d s 0v or 2.4v in capacitance meter dg421 dg423 dg425 figure 8. drain/source-off capacitance _________________________________timing diagrams/test circuits (continued) -15v v- r l gnd wr network analyzer signal generator +15v v+ 10nf rs +5v 50 w 0v or 2.4v 0v or 2.4v n.c. v l 10nf d in s s in dg421 dg423 dg425 d figure 7. crosstalk -15v v- gnd wr +15v v+ 10nf rs +5v v l 10nf d s 0v or 2.4v in capacitance meter dg421 dg423 dg425 figure 9. drain/source-on capacitance
dg421/dg423/dg425 improved low-power, cmos analog switches with latches _______________________________________________________________________________________ 9 _____________________________________________pin configurations (continued) 2120 d3 s3 n.c. s4 d4 18 17 16 15 14 wr d1 n.c. s1 in1 4 5 6 7 8 v- gnd n.c. v l v+ rs d2 n.c. s2 in2 319 13 9101112 dg423 dg425 plcc 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 s1 in1 v- gnd s3 d3 wr d1 dg423 dg425 v l v+ in2 s2 d2 rs d4 s4 dip _____________________________functional diagrams/truth tables (continued) wr rs in switch 1, 2 0 1 0 1 off on logic "o" 0.8v logic "1" 3 2.4v dg423 truth table d2 d1 ck d q two spdt switches per package s1 wr in1 in2 rs s2 dg423 s3 r q ck d q r q s4 d3 d4 switch 3, 4 on off d2 d1 ck d two dpst switches per package s1 wr in1 in2 rs s2 dg425 s3 r q ck d r q s4 d3 d4 wr rs in switch 01 0 1 off on logic "o" 0.8v logic "1" 3 2.4v dg425 truth table latch operation truth table wr rs in x1 x1 latch/switch x x x 0 0 x x latch operation transparent. control data latched in. switches on or off as selected by last in. all latches reset. switches on or off as when in = 0, wr = 0, rs = 1. top view n.c. = no internal connection
dg421/dg423/dg425 improved low-power, cmos analog switches with latches 10 ______________________________________________________________________________________ * contact factory for dice specifications. ** contact factory for availability and processing to mil-std-883b. _ordering information (continued) ___________________________________________________________chip topographies 0.105" (2.66mm) 0.082" (2.08mm) d1 s1 in1 n.c. n.c. n.c. n.c. d2 rs s2 in2 v- gnd vl v+ wr 0.105" (2.66mm) 0.082" (2.08mm) d1 s1 in1 d3 s3 s4 d4 d2 rs s2 in2 v- gnd vl v+ wr dg421 dg423 dg421 dg423/dg425 v l v l transistor count: 100 substrate connected to v+ transistor count: 100 substrate connected to v+ part temp. range pin-package dg423 cj 0? to +70? 16 plastic dip dg423cy 0? to +70? 16 so dg423dj -40? to +85? 16 plastic dip dg423dn -40? to +85? 20 plcc dg423ak -55? to +125? 16 cerdip** dg425 cj 0? to +70? 16 plastic dip dg425cy 0? to +70? 16 so dg425dj -40? to +85? 16 plastic dip dg425dn -40? to +85? 20 plcc dg425ak -55? to +125? 16 cerdip** dg423c/d 0? to +70? dice* dg423dy -40? to +85? 16 so dg423dk -40? to +85? 16 cerdip dg425c/d 0? to +70? dice* dg425dy -40? to +85? 16 so dg425dk -40? to +85? 16 cerdip
dg421/dg423/dg425 improved low-power, cmos analog switches with latches ______________________________________________________________________________________ 11 c a a2 e1 d e e a e b a3 b1 b dim a a1 a2 a3 b b1 c d d1 e e1 e e a e b l a min ? 0.015 0.125 0.055 0.016 0.050 0.008 0.745 0.005 0.300 0.240 ? 0.115 0? max 0.200 ? 0.150 0.080 0.022 0.065 0.012 0.765 0.030 0.325 0.280 0.400 0.150 15? min ? 0.38 3.18 1.40 0.41 1.27 0.20 18.92 0.13 7.62 6.10 ? 2.92 0? max 5.08 ? 3.81 2.03 0.56 1.65 0.30 19.43 0.76 8.26 7.11 10.16 3.81 15? inches millimeters 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc a1 l d1 e 21-587a a 16-pin plastic dual-in-line package ________________________________________________________package information c a d b1 b dim a b b1 c d e e1 e l l1 q s s1 a min ? 0.014 0.038 0.008 ? 0.220 0.290 0.125 0.150 0.015 ? 0.005 0? max 0.200 0.023 0.065 0.015 0.840 0.310 0.320 0.200 ? 0.060 0.080 15? min ? 0.36 0.97 0.20 ? 5.59 7.37 3.18 3.81 0.38 ? 0.13 0? max 5.08 0.58 1.65 0.38 21.34 7.87 8.13 5.08 ? 1.52 2.03 15? inches millimeters 2.54 bsc 0.100 bsc q l s1 e 21-590b 16-pin ceramic dual-in-line package a s l1 e e1
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1994 maxim integrated products printed usa is a registered trademark of maxim integrated products. dg421/dg423/dg425 improved low-power, cmos analog switches with latches dim a a1 a2 a3 b b1 c d d1 d2 d3 e min 0.165 0.100 0.145 0.020 0.013 0.026 0.009 0.385 0.350 0.290 max 0.180 0.110 0.156 ? 0.021 0.032 0.011 0.395 0.355 0.330 min 4.19 2.54 3.68 0.51 0.33 0.66 0.23 9.78 8.89 7.37 max 4.57 2.79 3.96 ? 0.53 0.81 0.28 10.03 9.02 8.38 inches millimeters 20-pin plastic leaded chip carrier package 21-981a d d1 d d1 d3 d2 e b1 b a3 a a1 a2 5.08 ref 0.200 ref 1.27 ref 0.050 ref c ___________________________________________package information (continued)

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